IEC 62050 Ed. 1.0 en:2005

VHDL Register Transfer Level (RTL) synthesis

International Electrotechnical Commission , 07/19/2005

Publisher: IEC

File Format: PDF

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Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.

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