Defines a mechanism for the test of core designs within a system on chip (SoC).This mechanism constitutes a hardware architecture and leverages the core test language (CTL)to faciliate communication between core designers and core integrators.
More Standards PDF
IEC 60191-6-13 Ed. 1.0 b:2007
$36.00 $73.00
IEC 61482-1-2 Ed. 1.0 b:2007
$103.00 $206.00
IEC 61158-6-3 Ed. 1.0 en:2007
$157.00 $314.00
IEC 62026-1 Ed. 2.0 b:2007
$41.00 $82.00