Defines a mechanism for the test of core designs within a system on chip (SoC).This mechanism constitutes a hardware architecture and leverages the core test language (CTL)to faciliate communication between core designers and core integrators.
More Standards PDF
IEC 61158-5-26 Ed. 2.0 en:2023
$227.00 $455.00
IEEE 2735.1-2022
$64.00 $129.00
IEC 60317-37 Ed. 2.1 En:2024
$106.00 $213.00
IEC 60502-4 Ed. 4.0 en:2023
$139.00 $278.00